@ARTICLE{Barkalov2024:i7687,
	author="{Barkalov, Alexander and Titarenko, Larysa and Bieganowski, Jacek and Krzywicki, Kazimierz}",
	title="{Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits—A Review}",
	year="2024",
	type="artykuł naukowy",
	language="en",
	journal="{Applied Sciences}",
	issn="2076-3417",
	volume="14",
	pages="2693(1)--2693(32)",
	doi="10.3390/app14072693",
	url="https://www.mdpi.com/2076-3417/14/7/2693",
	keywords="FPGAs; LUTs; EMBs; clock gating; decomposition; tate assignment; coarse-grained methods; fine-grained methods",
	abstract="{Methods for reducing power consumption in circuits of finite state machines (FSMs) are
discussed in this review. The review outlines the main approaches to solving this problem that
have been developed over the last 40 years. The main sources of power dissipation in CMOS
circuits are shown; the static and dynamic components of this phenomenon are analyzed. The
power consumption saving can be achieved by using coarse-grained methods common to all digital
systems. These methods are based on voltage or/and clock frequency scaling. The review shows
the main structural diagrams generated by the use of these methods when optimizing the power
characteristics of FSM circuits. Also, there are various known fine-grained methods taking into
account the specifics of both FSMs and logic elements used. Three groups of the fine-grained methods
targeting FPGA-based FSM circuits are analyzed. These groups include clock gating, state assignment,
and replacing look-up table (LUT) elements by embedded memory blocks (EMBs). The clock gating
involves a separate or joint use of such approaches as the (1) decomposition of FSM inputs and (2)
disabling FSM inputs. The aim of the power-saving state assignment is to reduce the switching
activity of a resulting FSM circuit. The replacement of LUTs by EMBs allows a reduction in the power consumption due to a decrease in the number of FSM circuit elements and their interconnections. We hope that the review will help experts to use known methods and develop new ones for reducing power consumption. We think that a good knowledge and understanding of existing methods of reducing power consumption is a prerequisite for the development of new, more effective methods to solve this very important problem. Although the methods considered are mainly aimed at FPGA- based FSMs, they can be modified, if necessary, and used for the power consumption optimization of FSM circuits implemented with other logic elements.}",
}